This invention involves improvements in printed circuit boards and relates specifically to those types of printed circuit boards which bear multiple conductor arrays.
With the constant trend toward miniaturization of electronic components and especially the use of integrated circuitry and integrated circuit chip components which are mounted on printed circuit boards, there is a constant trend toward finding methods of increasing the density of components while minimizing the amount of real estate or printed circuit board area involved both in length, width and also thickness.
There is increasingly a trend toward the use of multilayer printed circuit boards whereby conductive material is separated by insulative material and several layers of such materials are interleaved in order to provide multiple capabilities of interconnection between the electronic components which are mounted on the outer area of the printed circuit board.
By the use of plated-through apertures or "vias", it is possible to interconnect various of the conductive materials on the different layers of the printed circuit board and at the same time, wheh necessary, provide insulation when the interconnected elements must not contact a certain layer of the interpenetrating via or aperture.
Accordingly, such patents as U.S. Pat. No. 4,362,899 entitled "Printed Circuit Board" indicates types of elements of the construction of multilayered conductive material separated by layers of insulating material and the use of "plated-through holes". Mention here is also made of a ground plane whereby certain shield tracks are connected to the ground plane to provide shielding.
Similarly, U.S. Pat. No. 4,328,531 entitled "Thick Film Multilayer Substrate" involves a technique of construction of multiple conductor layers with dielectric layers interleaved between them. Here, a power supply line is formed in the conductor layer and is interposed between the first and third conductor layers.
It has been found desirable in the design of high density printed circuit boards, which involve the mounting of multiple components, to provide not only voltage and ground connections to various of the electronic components mounted thereon, but it is also necessary to provide interleaved conductive layers to provide connections between various components with each other, and various components with the voltage plane and the ground plane. Further, in order to minimize signal distortion of pulses or waves traveling in the printed circuit conductors, it is most desirable to maintain a constant impedance between various conductors referenced to the voltage plane and ground plane.
To this end, the present disclosure indicates the development of a high density element storage capability on a printed circuit board involving a plurality of conductive layers which may involve up to six conductive layers separated by insulating substrate and wherein there is provided a constant impedance parameter of 100 ohms plus or minus 10% between any conductive line and the voltage plane and between any conductive line and the ground plane of the printed circuit board. This impedance level is a standard requirement for Transistor-Transistor Type (TTL) logic. In addition, there is a standard constraint thickness of printed circuit boards which requires overall thickness of 0.062.+-.0.007 inch (7 mils). Thus, the overall thickness of the printed circuit board may be permitted up to a maximum of 0.069 inches (69 mils).